Manager / Senior Manager – Design Verification
Core
Lead and develop a high-performing Design Verification team responsible for IP and SoC verification across multiple projects, driving planning, execution, and closure.
Role type
Senior Manager, Design Verification
Builds
Robust IP and SoC solutions for smart home, industrial IoT, and smart cities markets
Domain
Semiconductor / VLSI / Embedded Systems
Deliverable
production ML models | product features
Required skills
SystemVerilog, UVM, assertions, constrained-random verification, functional coverage, regression management, verification planning, testbench architecture, debug methodologies, resource allocation, cross-functional collaboration, team leadership, mentoring
Preferred skills
Formal verification, emulation, FPGA prototyping, performance verification, hardware-software co-verification, low-power verification (UPF), reusable UVM environments, verification IP, automation frameworks, Python, Perl, Tcl, AI-assisted verification tools
Technologies
SystemVerilog, UVM, Python, Perl, Tcl
Responsibilities
Lead and develop a high-performing Design Verification team; Drive verification planning, execution, functional coverage closure, regression management, sign-off, and on-time delivery; Provide technical leadership in SystemVerilog, UVM, assertions, constrained-random verification, and debug methodologies; Manage project priorities, technical risks, resource allocation, and dependencies; Collaborate with Design, Architecture, Firmware, Validation, and Program Management teams; Define and drive verification strategies for complex IPs, subsystems, and SoCs; Drive continuous improvements in verification methodologies, automation, and reusable infrastructure; Mentor engineers and develop technical leaders; Establish execution metrics and monitor project progress; Support hiring, performance management, and career development.
Seniority
Senior Manager, hands-on IC with people leadership
