ASIC Digital Design Engineer
Core
Own RTL design and subsystem integration for digital logic in high-performance silicon photonics integrated circuits (100G, 200G, 400G per lambda solutions).
Role type
Senior IC ASIC Digital Design Engineer
Builds
Silicon photonics integrated circuits and CPO (Co-Packaged Optics) engines
Domain
Semiconductor / Silicon Photonics / Optical Interconnects
Deliverable
production ML models | product features
Required skills
RTL design (Verilog/SystemVerilog), ASIC/SoC design flow, digital integration, DFT, mixed-signal interface design, high-speed interface circuitry, Python/Perl/Tcl/Shell scripting, low-power design (UPF/CPF), FPGA prototyping
Preferred skills
Master's degree in EE, technical leadership, post-silicon validation support, ATE enablement
Technologies
Verilog, SystemVerilog, UPF, CPF, SerDes, D2D IP
Responsibilities
Own RTL design of complex digital blocks and subsystems; Drive RTL design and integration for control functions and high-speed interfaces; Review RTL quality and coding standards; Document design specifications and implementation plans; Collaborate with verification teams for test plans and coverage; Support synthesis, timing closure, and power optimization; Develop automation scripts for design checks and QoR tracking; Debug simulation and integration issues; Support firmware/C coding for CPU subsystems; Partner with post-silicon teams on bring-up and production readiness.
Seniority
Senior, hands-on IC
