Senior ASIC Engineer
Core
Defines, architects, designs, and verifies high-performance ASICs for Cisco's core Switching, Routing, and Wireless products.
Role type
Senior IC ASIC Design and Verification Engineer
Builds
High-performance ASICs for AI-era networking hardware
Domain
Semiconductor / Networking
Deliverable
production ML models | product features
Required skills
ASIC design and verification, System Verilog, debugging, UVM, emulation platforms, power optimization, block-level design, chip-level issue resolution
Preferred skills
Dashboard management for regression/coverage, post-silicon lab bring-up, Linux/C/C++/Python/Perl, Networking
Technologies
System Verilog, UVM, Veloce, Palladium, Zebu, HAPS, Linux, C, C++, Python, Perl
Responsibilities
Drive definition, architecture, design, and verification of high-performance ASICs; Own complex or multiple functional areas; Develop and create reusable code; Debug at ASIC, SW, HW level; Lead design and DV work by solving block level issues; Define new verification methodologies; Identify, design, and implement power saving solutions
Seniority
Senior, hands-on IC
