ASIC Engineering Technical Leader
Core
Define, design, and verify high-performance ASIC subsystems for Cisco's next-generation networking platforms, focusing on analog and mixed-signal circuits.
Role type
Senior IC ASIC Engineering Technical Leader
Builds
High-volume, premium-quality ASIC subsystems for Cisco platforms
Domain
Networking silicon, high-frequency CMOS, analog and mixed-signal circuit design
Deliverable
production ML models | product features
Required skills
High-frequency CMOS circuit design, custom analog and mixed-signal circuit design, Cadence Virtuoso (custom layout, DRC, LVS, parasitic extraction), programming in Skill/VerilogA/Tcl/Perl/Python/Matlab/C
Preferred skills
High-speed wireline SerDes design, signal processing, digital design flow (synthesis and P&R), EM field simulation (EMX, Momentum, HFSS), packaging technology, measurement equipment usage
Technologies
Cadence Virtuoso, Skill, VerilogA, Tcl, Perl, Python, Matlab, C, Siemens/Mentor, Synopsys, EMX, Momentum, HFSS, Jira
Responsibilities
Define and design high-performance ASIC subsystems, oversee architecture of complex analog and mixed-signal circuits, establish robust verification strategies, collaborate on packaging and hardware requirements, guide development of reusable code methodologies and physical design functions
Seniority
Senior, hands-on IC with significant leadership responsibilities