CareerPlanGet AI match score →

ASIC Engineering Technical Leader (Onsite)

San Jose, California, US💼 Full-time💰 $210,600–$210,600🗓 2026-06-01 → 2026-07-31

Core

Conduct root cause failure analysis of silicon product reliability test and field failures to propose corrective actions.

Role type

Senior IC Failure Analysis Engineer (Semiconductor)

Builds

Reliability and yield solutions for ASIC products

Domain

Semiconductor manufacturing and reliability engineering

Deliverable

production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work

Required skills

Semiconductor failure analysis techniques, Root cause analysis, Cross section, X-ray, CSAM, TDR, FIB, SEM, TEM, IR/EMMI/OBIRCH, Solid Immersion Lens (SIL), Laser Scanning Microscopy (LSM), ATE test data interpretation, Fault isolation techniques, JEDEC IC Qualification tests

Preferred skills

Semiconductor technology and process knowledge (Fab, Assembly, Advanced Packaging), Transistor function and device physics, ATE test data categorization, Physical failure analysis with suppliers, Emerging technology fault characterization

Technologies

ATE, Scan/ATPG, MBIST, SIL, LSM, Cross section, X-ray, CSAM, TDR, FIB, SEM, TEM, IR/EMMI/OBIRCH

Responsibilities

Conduct root cause failure analysis of silicon product reliability test and field failures, Develop and implement standard processes for failure analysis, Coordinate logistics and instructions for the failure analysis process, Document and report failure analysis results, Function as a technical resource for failure analysis questions, Develop and maintain relationships with FA service and equipment vendors

Seniority

Senior, hands-on IC

Sourced via workday · Listed on CareerPlan, which tracks 70,000+ jobs from 20+ sources.
Apply on Workday ↗