ASIC Packaging Signal Integrity Hardware Engineering Technical Lead (Remote)
Core
Lead signal and power integrity engineering for next-generation ASIC packaging, defining design rules and analyzing substrate integrity for high-performance silicon devices.
Role type
Senior IC hardware engineering technical lead (signal/power integrity)
Builds
Complex ASIC packages and silicon devices for Cisco's unified routing and switching portfolio
Domain
Semiconductor hardware engineering, high-speed ASIC packaging, 2.5D fanout technologies
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Signal integrity (SI) analysis, Power integrity (PI) analysis, High-speed SerDes architectures (56G PAM4+), Channel modeling, Electromagnetics, Transmission line theory, Keysight ADS, Ansys HFSS/EM, Cadence APD, SPICE, IC architecture definition, Technical mentorship
Preferred skills
Team leadership, Advanced process nodes (5nm/3nm), High-bandwidth memory (HBM) interfaces, Die-to-die interfaces (UCIe), Advanced packaging (CoWoS, EMIB, interposer), MATLAB/Python scripting, Vector Network Analysis, IBIS
Technologies
Keysight ADS, Ansys HFSS/EM, Cadence APD, MATLAB, Python, Raptor-X
Responsibilities
Develop and implement design rules for ultra-high-speed signaling, Analyze substrate signal and power integrity, Design and document ASIC packages for high-volume release, Collaborate with system partners to resolve complex technical issues, Define processes and tools for complex ASIC/package development, Mentor signal integrity team and influence packaging teams
Seniority
Senior, hands-on IC with mentorship responsibilities
