Principal Signal Integrity Engineer
Core
Technical authority responsible for electrical integrity of high-performance AI compute platforms, ensuring stable, manufacturable hardware for Digital In-Memory Computing architecture.
Role type
Senior Staff IC Signal Integrity/Power Integrity Engineer
Builds
Next-generation AI accelerators with 112G/224G SerDes and multi-chip modules (MCM)
Domain
AI hardware, high-speed interconnects, chiplet-to-chiplet design
Deliverable
production ML models
Required skills
SI/PI strategy for high-speed interfaces, MCM & package simulation, PDN architecting, link analysis & budgeting, lab correlation & measurement, constraint management for PCB layout, technical mentorship
Preferred skills
PCB material science modeling, Python/MATLAB for simulation automation, OCP hardware specifications
Technologies
Ansys HFSS, Cadence Sigrity, Keysight ADS, Simbeor, Ansys SIwave, Cadence PowerSI, CST, IBIS-AMI, VNA, TDR, high-speed oscilloscopes
Responsibilities
Drive SI/PI strategy for next-gen AI accelerators focusing on PCIe Gen6/7, CXL, LPDDR5, and custom interconnects; Lead modeling and analysis of complex multi-chip packages including interposer routing and die-to-die link budgeting; Design and optimize Power Delivery Networks to meet Z_Target requirements; Perform comprehensive channel simulations using IBIS-AMI models to define jitter, crosstalk, and loss budgets; Lead lab validation correlating simulation results with VNA, TDR, and oscilloscope measurements; Translate simulation findings into actionable physical layout constraints for PCB design teams; Act as subject matter expert guiding hardware and layout engineers on SI/PI best practices
Seniority
Senior Staff, hands-on IC with mentorship
