ASIC Engineering Digital Designer/ Leader ( digital design, FSM, CPU sub-systems, complex SOCs, FPGA validation | 8-12 Years | Pune)
Core
Digital Design Lead responsible for defining digital architecture, RTL design of CPU subsystems and data path interfaces, and full-chip integration for high-speed optical interconnects (100G, 200G, 400G) in silicon photonics and Co-Packaged Optics (CPO).
Role type
Senior IC ASIC Digital Design Lead
Builds
High-performance optical transceivers and silicon photonic platforms for data center networking
Domain
Silicon Photonics / Optical Interconnects / ASIC Design
Required skills
RTL design (SystemVerilog), CPU subsystem design, FSM design, complex SoC design, FPGA validation, SerDes integration, DFT, synthesis, timing closure, CDC/RDC, verification coverage analysis
Preferred skills
Master's degree in EE, experience with 800G/1.6T optical modules, knowledge of SPI/I2C/AXI protocols, low power design, design automation scripting
Technologies
SystemVerilog, FPGA, SerDes, DFT tools, Synthesis tools, LEC, ATE
Responsibilities
Define digital architecture and interface requirements; own block-level and top-level design and verification; support full-chip integration of high-speed IPs; review verification coverage and sign off on metrics; support backend activities including synthesis, timing closure, and DFT; contribute to FPGA prototyping and lab validation.
Seniority
Senior, hands-on IC
