ASIC Engineering Digital Designer/ Leader ( digital design, FSM, CPU sub-systems, complex SOCs, FPGA validation | 8-12 Years | Pune)
Core
Lead digital design for silicon photonics and high-speed optical interconnects (100G-400G), defining architecture and implementing CPU subsystems and data path interfaces for Co-Packaged Optics.
Role type
Senior IC ASIC Digital Design Lead (Silicon Photonics)
Builds
High-speed optical transceivers, silicon photonic platforms, and Co-Packaged Optics (CPO) modules.
Domain
Data Center Networking / Silicon Photonics / High-Speed Optical Interconnects
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Digital design (FSM, CPU subsystems, complex SOCs), ASIC/SoC design flow, SystemVerilog, RTL development, SerDes, FPGA validation, DFT, synthesis, timing closure, low power design, verification coverage analysis
Preferred skills
Master's degree in EE/Electronics, experience with 800G/1.6T optical modules, expertise in high-speed protocols (SPI, I2C, AXI, Ethernet, D2D PHY)
Technologies
SystemVerilog, FPGA, GDS2, CDC/RDC, LEC, DFT tools, SerDes IP, DSP IP
Responsibilities
Define digital architecture and interface requirements for optical interconnects; own block-level and top-level design and verification; support full-chip integration of high-speed IPs; review verification coverage and sign off on metrics; support backend activities including synthesis, timing closure, and low power design; contribute to FPGA prototyping and lab validation.
Seniority
Senior, hands-on IC
