ASIC Layout Engineer - Analog, High speed IP - 8 to 11 years - Bangalore
Core
Physical implementation of high-performance analog and mixed-signal circuits for next-generation 100G, 200G, and 400G per lambda optical interconnect solutions.
Role type
Senior IC ASIC Layout Engineer (Analog/Mixed-Signal/High-Speed)
Builds
Block-level layouts for SerDes, PAM4 interfaces, clocking subsystems, and control logic
Domain
Semiconductor IC Design / Optical Interconnects
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Custom IC layout design, physical verification, parasitic-aware implementation, matching, symmetry, shielding, signal integrity, thermal management, DRC/LVS/ERC compliance, tapeout processes, Linux environments, scripting (Python/Perl/TCL)
Preferred skills
Master's degree in EE, experience with top-level integration, familiarity with ASIC/SoC tapeout processes, experience with layout automation
Technologies
Cadence Virtuoso, Calibre
Responsibilities
Support layout development and physical implementation of analog, mixed-signal circuits, and high-speed interfaces; Participate in block-level floorplanning, placement, routing, and integration; Collaborate with circuit designers to translate schematics into optimized physical layouts; Optimize layouts for electrical performance, matching, parasitics, signal/power integrity, thermal behavior, yield, and manufacturability; Ensure compliance with all foundry design rules (DRC, LVS, ERC, density, EM/IR, and reliability requirements); Assist in integration across analog, digital, and high-speed domains; Review post-layout extraction results and support simulation closure; Partner with packaging and product teams on bump planning, pad ring, ESD structures, and package integration; Identify and help resolve layout-related issues impacting performance, yield, or production readiness; Participate in layout reviews and provide input on feasibility, tradeoffs, and tapeout risks; Collaborate with CAD teams to improve layout flows, automation, and productivity; Support tapeout readiness, including database checks and signoff; Assist senior engineers with mentoring more junior layout team members; Support silicon bring-up, debug, and failure analysis for layout-related issues
Seniority
Senior, hands-on IC with mentorship responsibilities
