ASIC Engineering Layout Leader
Core
Lead end-to-end physical implementation of high-performance analog, mixed-signal, and high-speed circuits (SerDes, PAM4) from concept through tapeout for Cisco's next-generation optical interconnect solutions.
Role type
Senior IC ASIC Layout Lead
Builds
Custom silicon solutions for 100G, 200G, and 400G per lambda optical interconnect technologies
Domain
Semiconductor IC Design / High-Speed Analog & Mixed-Signal / Optical Interconnects
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Custom IC layout (analog, mixed-signal, high-speed), Block-level and top-level floorplanning, Placement and routing, Physical verification (DRC, LVS, ERC, EM/IR), Parasitic-aware design, Tapeout readiness, Cross-functional technical leadership, Mentorship
Preferred skills
Advanced-node layout (FinFET, GAA), Signal integrity and power integrity optimization, Thermal behavior analysis, SerDes/PAM4 interface design, Python/Perl/TCL scripting for automation, Linux environment proficiency
Technologies
Cadence Virtuoso, Linux
Responsibilities
Lead end-to-end layout development for complex analog, mixed-signal, and high-speed circuits; Own block-level and top-level floorplanning, placement, routing, and integration; Translate circuit schematics into optimized, manufacturable layouts; Optimize designs for parasitics, matching, signal integrity, power integrity, thermal behavior, and yield; Ensure compliance with physical verification requirements; Drive integration across analog, digital, and high-speed domains; Support post-layout extraction, simulation closure, and tapeout readiness; Partner with packaging teams on bump planning and package integration; Mentor junior engineers and strengthen layout best practices; Support silicon bring-up, debug, and failure analysis
Seniority
Senior, hands-on IC with technical leadership
