ASIC - Signal and Power Integrity Technical Leader - 10 to 16 Years - Bangalore/Chennai
Core
Lead Signal and Power Integrity (SI/PI) for next-generation ASIC packaging and heterogeneous system integration, ensuring power, performance, and area goals for high-speed silicon devices.
Role type
Senior IC Technical Leader (Signal and Power Integrity)
Builds
Complex ASICs and 2.5D/3D packaging solutions for Cisco's unified routing and switching portfolio (TOR switches to web-scale data centers).
Domain
Semiconductor / High-Speed ASIC Design / Advanced Packaging
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Signal Integrity (SI), Power Integrity (PI), high-speed SerDes architectures, channel modeling, BER prediction, transmission line theory, electromagnetics, scattering and impedance network parameters, post-layout extraction, design rule development, IC and analog/mixed-signal circuit design reviews, team mentorship
Preferred skills
Advanced node design (5nm, 3nm), high-bandwidth memory (HBM) interfaces, die-to-die interfaces (UCIe), advanced packaging (CoWoS, EMIB, interposer-based), MATLAB or Python scripting, Vector Network Analysis, IBIS
Technologies
Keysight ADS, Ansys HFSS/EM flow, Cadence APD, SPICE, MATLAB, Python, Raptor-X
Responsibilities
Develop and implement design rules for ultra-high-speed signaling; analyze substrate SI/PI and collaborate with layout teams; design and document ASIC packages for high-volume release; resolve complex technical issues using advanced technology design rules; define processes and tools for complex ASIC/package developments; lead chip architecture discussions and design reviews; mentor junior engineers and influence packaging/hardware teams
Seniority
Senior, hands-on IC with leadership responsibilities
