Hardware SI/PI Engineering Senior Technical Leader | SI/PI, PCB, Package, VNA, TDR, HFSS, ADS, Allegro, PAM4 SERDES | 12+ years, Bangalore
Core
Design and analyze high-speed interconnects and power distribution networks for Cisco's next-generation Switch, Router, and AI/ML platforms.
Role type
Senior Technical Lead, Signal & Power Integrity (SI/PI)
Builds
High-speed networking and compute systems (Switches, Routers, AI/ML platforms)
Domain
Networking hardware, high-speed digital design, electromagnetics
Deliverable
production ML models | product features
Required skills
Electromagnetics fundamentals, transmission line theory, VNA/TDR measurement, circuit-level simulation, system-level simulation, cross-functional collaboration, technical mentorship
Preferred skills
HFSS, ADS, Allegro, PowerSI/DC, MATLAB, Simbeor, HSpice, PAM4 SerDes, high-speed PCB/package layout, power integrity optimization, optical transceiver modules
Technologies
HFSS, ADS, Allegro, PowerSI/DC, MATLAB, Simbeor, HSpice, VNA, TDR, high-bandwidth oscilloscope
Responsibilities
Model and simulate high-speed links (SerDes, IC package, system interconnects); Analyze and model power delivery networks and perform EM modeling of complex 3D structures; Lead pre- and post-layout signal integrity analysis for PCB and package designs; Define stack-up strategy, PCB materials, and collaborate with vendors on DFM; Write SI/PI design guidelines, test plans, and validation reports; Support prototype bring-up, validation, and troubleshooting in the lab; Mentor and guide junior SI/PI engineers; Drive continuous improvement of simulation flows and design processes; Lead system-level investigations spanning ASIC, package, and board domains; Contribute to SI/PI technology roadmap
Seniority
Senior, hands-on IC with mentorship responsibilities
