ASIC Link Modeling Technical Leader
Required skills
Python, C/C++, MATLAB, high-speed communication theory, transmission line theory, SerDes, Ethernet, D2D PHY protocols, DSP fundamentals, EDA and SI simulation tools, link modeling methodologies, analytical skills, problem-solving skills, debugging skills, communication skills, teamwork abilities
Preferred skills
optical DSP (ODSP), integrated transceiver features, PAM4 modulation techniques, IBIS-AMI model development, Linux-based development environments, scripting automation (Perl, TCL), ASIC/SoC design flow knowledge, post-silicon validation experience
Technologies
Cisco, Silicon Photonics, IM/DD optics, Co-packaged Optics (CPO), 800G, 1.6T, 100G, 200G, 400G per Lambda, SerDes, optical DSP (ODSP), die-to-die (D2D) interfaces, Keysight ADS, Synopsys HSPICE, Cadence, IBIS-AMI, FFE, CTLE, DFE, Ethernet
Responsibilities
Develop system-level behavioral models, create comprehensive link simulations, lead link budget analysis, perform channel modeling, conduct statistical simulations, evaluate jitter, noise, crosstalk, and bit error rate (BER), define and optimize transceiver architectures, debug complex link simulations, identify architectural bottlenecks, correlate pre-silicon models with post-silicon lab measurements, collaborate across cross-functional teams, develop IBIS-AMI models, create modeling documentation, support product release from concept through production
Seniority
Technical Leader, 12+ years experience (Bachelor's), 8+ years experience (Master's), 5+ years experience (PhD)
Domain
Silicon Photonics, Optical Transceivers, Data Center Networking, High-Speed Communication