ASIC Link Modeling Technical Leader
Core
Develop system-level behavioral models and comprehensive link simulations for Cisco's silicon photonics systems, enabling performance analysis across high-speed SerDes, optical DSP, and die-to-die interfaces for next-generation 100G/200G/400G per Lambda solutions.
Role type
Senior IC ASIC Link Modeling Technical Leader
Builds
High-speed optical transceivers, silicon photonic platforms, and Co-packaged Optics (CPO) for data center networking
Domain
Data center networking, Silicon Photonics, High-speed SerDes
Deliverable
production ML models | product features
Required skills
Python, C/C++, MATLAB, high-speed communication theory, transmission line theory, SerDes, Ethernet, D2D PHY protocols, DSP fundamentals, EDA tools (Keysight ADS, Synopsys HSPICE, Cadence), link modeling methodologies
Preferred skills
Optical DSP (ODSP), integrated transceiver features, PAM4 modulation, IBIS-AMI model development, Linux-based development environments, scripting automation (Perl, TCL), ASIC/SoC design flow, post-silicon validation
Technologies
Keysight ADS, Synopsys HSPICE, Cadence, Python, C/C++, MATLAB, Perl, TCL
Responsibilities
Develop system-level behavioral models and link simulations; Lead link budget analysis, channel modeling, and statistical simulations; Define and optimize transceiver architectures including TX/RX equalization and DSP algorithms; Debug complex link simulations and correlate pre-silicon models with post-silicon lab measurements; Collaborate to develop IBIS-AMI models and support product release
Seniority
Senior, hands-on IC