ASIC Design Engineer - Pixel IP ANE
Core
Designing high-speed, high-performance subsystems for the next-generation Apple Neural Engine (Pixel IP ANE) to enable AI/ML capabilities in consumer products.
Role type
Senior IC ASIC Design Engineer (Pixel IP ANE)
Builds
Next-generation Apple Neural Engine hardware
Domain
Consumer electronics / AI/ML hardware acceleration
Deliverable
production ML models
Required skills
RTL design, computer architecture, AMBA protocols, design verification, formal verification, physical design, static timing analysis, clock domain crossing analysis, DFT, BIST, synthesis, power intent
Preferred skills
Large high-speed compute system experience, extensive AMBA bus topology knowledge
Technologies
AMBA, RTL, Synthesis, Static Timing Analysis, DFT, BIST
Responsibilities
Perform RTL design on high-speed, high-performance subsystems; collaborate with verification teams to ensure design correctness and performance; work with physical design and timing teams to produce high-quality netlists; analyze clock domain crossing designs; coordinate with DFT and BIST teams for full testability.
Seniority
Mid-level IC Engineer (BS + 3 years)
