ASIC Design and Integration Engineer – Silicon Security
Core
Designing and integrating secure hardware subsystems (cryptographic engines, side-channel monitors) to protect Apple SoCs from attacks.
Role type
Senior ASIC Design Engineer (Silicon Security)
Builds
Secure RTL blocks and integrated subsystems for Apple SoCs
Domain
Consumer electronics / Hardware Security
Required skills
RTL design (Verilog/SystemVerilog), micro-architecture, IP integration, CDC/RDC analysis, UPF, synthesis, timing closure, AMBA protocols (AXI/AHB/APB), cryptographic algorithm implementation, hardware security concepts (key management, physical attack countermeasures)
Preferred skills
AI-assisted design tools, low-power design techniques, clock and reset architecture at subsystem level
Responsibilities
Architecting and designing state-of-the-art security features; Integrating security IPs into secure subsystems; Resolving integration issues across multiple IP blocks; Driving front-end quality flows from RTL to netlist
Seniority
Senior, hands-on IC
