Physical Design Engineer
Core
Physical Design Engineer responsible for high-performance PHY design from RTL to GDSII delivery, collaborating with architecture, CAD, timing, and logic teams.
Role type
Senior IC Physical Design Engineer (PHY/SOC)
Builds
High-performance PHY and SOC chips
Domain
Semiconductor / Hardware Design
Required skills
Static timing constraints, floor-planning, place and route, clock network design, power grid design, ECO generation, LVS/DRC verification, scripting (Perl/Tcl), SoC architecture, HDL (Verilog), Physical Design & Synthesis tools
Preferred skills
High PHY/SOC design experience, physically aware synthesis, clock/power specification development, physical verification methodology, chip integration flow
Technologies
Perl, Tcl, Verilog, industry standard Physical Design & Synthesis tools
Responsibilities
Generate block/chip level static timing constraints; Build full chip floor-plan including pin placement, partitions and power grid; Develop and validate high performance low power clock network guidelines; Perform block level place and route and close the design to meet timing, area and power constraints; Generate and Implement ECOs to fix timing, noise and EM IR violations; Run Physical Design verification flow at chip/block level and provide guidelines to fix LVS/DRC violations
Seniority
Senior, hands-on IC
