ESD Engineer
Core
Define ESD methodology and design protection circuits to ensure silicon immunity to ESD and latch-up events for Apple's ICs.
Role type
Senior IC ESD Engineer
Builds
High-quality on-chip IPs immune to ESD/EOS and latchup events
Domain
Semiconductor design / ESD protection
Required skills
ESD circuit design, transistor device characteristics, ESD test models (HBM, CDM, MM, IEC-61000-4-2), EDA tools (Virtuoso, Calibre, Allegro), ESD/LUP test equipment operation
Preferred skills
MS degree, state-of-the-art ESD topology knowledge, debug activities leadership
Technologies
Virtuoso, Calibre, Allegro
Responsibilities
Define ESD methodology for all silicon, design ESD protection devices and circuits, develop test structures for ESD/LUP characterization, drive ESD/LUP related debug activities
Seniority
Senior, hands-on IC
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