SoC Physical Design Engineer, PnR
Core
Physical implementation of design partitions from netlist to tapeout for highly complex SoCs.
Role type
SoC Physical Design Engineer (PnR)
Builds
SoC chips
Domain
Semiconductor / VLSI
Required skills
netlist to GDS2 implementation, timing signoff closure, physical and electrical verification, floor-planning, place and route (PnR), power grid design, DRC/LVS verification, EMIR analysis
Preferred skills
Verilog, VHDL, Python, Perl, TCL, SPICE, computer architecture knowledge, VLSI design
Technologies
Redhawk, Totem, Voltus, SPICE
Responsibilities
Collaborate with architecture, CAD, timing, and logic design teams; drive physical aspects early in the design cycle; resolve and improve design and flow issues related to physical design.
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