ASIC Design Engineer - Cache Controller
Core
Design and develop hardware for cache subsystems in high-performance System on a Chip (SoC), focusing on micro-architecture, RTL design, and timing closure.
Role type
Senior IC ASIC Design Engineer (Cache Controller)
Builds
Special-purpose cache and controller components for mobile SoC memory hierarchy
Domain
Semiconductor / Hardware Design
Required skills
ASIC design, RTL design, micro-architecture definition, PPA analysis, cache design, multi-processor cache coherence protocols, memory system development
Preferred skills
High-performance coherent memory systems, interconnect architectures, high-performance DRAM controller
Technologies
RTL, SoC, cache subsystems, netlist, timing closure
Responsibilities
Develop cache micro-architecture based on guidelines and model analysis; Explore architecture trade-offs in performance, area, and power; Develop and debug RTL design of cache subsystem sections; Work on front-end netlist and area/timing analysis; Collaborate with physical design team on timing closure
Seniority
Senior, hands-on IC
