Analog Simulation/Env Automation CAD Engineer
Core
Develop, maintain, and enhance custom analog power intent methodology and circuit ERC solutions for transistor-level analysis on analog, RF, and mixed-signal designs.
Role type
Senior IC analog simulation and EDA automation engineer
Builds
Custom SPICE simulation flows, design environment enhancements, and results analysis tools for analog/RF/mixed-signal circuits
Domain
Semiconductor hardware design (analog, RF, mixed-signal)
Required skills
SPICE simulation (Spectre, Hspice, ADS), EDA automation scripting (Perl, Python, TCL, SKILL, Shell), transistor-level analysis, waveform analysis, netlist processing, PDK qualification, Verilog-A/AMS
Preferred skills
Cadence ADE (XL, Maestro, OCEAN), Virtuoso environment, statistical simulations (Monte Carlo, PVT), reliability/aging analysis, SOA checks, ERC asserts, behavioral RTL/AMS circuits, Post-layout extraction, Perforce version control
Technologies
Virtuoso, ADE-XL, Maestro, OCEAN, Spectre, Hspice, ADS, SKILL, Python, Perl, TCL, Shell, Verilog-A, AMS
Responsibilities
Solve transistor-level simulation issues using Spice simulators on command-line and Virtuoso; guide designers in resolving Analog Design Environment (ADE/XL, Maestro, OCEAN) issues and develop automation flows; steer methodology on SPICE simulation and modeling techniques; architect and develop next-generation in-house EDA CAD flow solutions
Seniority
Senior, hands-on IC
