SerDes System Validation Engineer
Core
Lead system validation, bring-up, and debug of mixed-signal SerDes IP for Apple's SoC and PHY products.
Role type
Senior IC system validation engineer (SerDes)
Builds
High-speed serial link IP for consumer electronics
Domain
Semiconductor / Analog-Mixed Signal / High-Speed Serial Links
Required skills
SerDes system bring-up and validation, mixed-signal verification, high-speed serial link protocols (PCIe, USB, UCIe, OIF), system-level DFT definition, scripting for automation (Python, C, Matlab), silicon bring-up and debug, link jitter budget analysis, Tx/Rx equalization techniques, ADC-based link knowledge, PCB design specifications
Preferred skills
Creative problem solving for system validation, leading mixed-signal SerDes validation teams, experience with production ramp
Technologies
PCIe, USB, UCIe, OIF, Python, C, Matlab, CDR, Equalization
Responsibilities
Perform SerDes bring-up in system environment and verify basic operations, analyze robustness and margins, collaborate with design teams to define DFT needs, execute mixed-signal verification tasks, lead system validation efforts, support silicon bring-up and production ramp
Seniority
Senior, hands-on IC