DRAM Design Validation Engineer
Core
Ensuring successful integration of DRAM memories with SoC devices and validating memory controller and PHY requirements.
Role type
DRAM Design Validation Engineer
Builds
Apple's main memory features for next-generation high-performance SoCs
Domain
Semiconductor / Memory / SoC
Required skills
DRAM cell architecture, DRAM memory organization, DRAM simulation, memory interface verification, DDR-PHY characterization, LPDDR IO qualification, memory test patterns, DRAM reliability, innovative packaging technology, Failure Analysis, hardware/software debug, C/C++ programming
Preferred skills
Expertise in low power DRAM design, LPDDR IO characterization, memory test patterns, DRAM reliability, innovative packaging technology, Failure Analysis, computer architecture, C/C++ programming
Technologies
DDR/DDR2/DDR3/DDR4/DDR5, LPDDR, POP, TSV, C/C++
Responsibilities
Define memory controller and PHY requirements covering DRAM corner cases; Collaborate with Architecture, MCU, DDRPHY, and DRAM vendors; Ensure DRAM simulation meets requirements; Meet internal and external DRAM silicon and package level testing needs; Debug RMA material with apparent DRAM related defects
Seniority
Mid-Senior, hands-on IC