Design Verification Engineer - Fabric Interconnect
Core
Own integration-level verification of Fabric Top, including coherency (CHI), PCIe/CXL traffic, and configuration access traffic.
Role type
Senior IC design verification engineer (fabric interconnect)
Builds
Verification environments and test plans for fabric interconnects and protocol bridges
Domain
Semiconductor / Hardware Verification
Required skills
UVM, System Verilog, Python, Formal methods, Generative AI, CHI, PCIe, CXL, AMBA, IP verification, Test plan development, Debugging, Coverage signoff
Preferred skills
Automation, AI-based verification approaches, Mentoring
Technologies
UVM, System Verilog, Python, CHI, PCIe, CXL, AMBA
Responsibilities
Define verification strategies and test plans; Develop and debug UVM/System Verilog verification environments; Run simulations and drive quality; Apply formal methods and AI tools; Mentor team members; Lead verification of designs using CHI and AMBA protocols.
Seniority
Senior, hands-on IC
