Senior/Principal Power and Signal Integrity Engineer
Core
Define and drive power integrity and signal integrity strategy for next-generation Cryo-CMOS quantum control systems, ensuring electrical integrity across silicon, package, PCB, and system levels.
Role type
Senior/Principal Power and Signal Integrity Engineer
Builds
Next-generation Cryo-CMOS quantum control systems
Domain
Quantum computing hardware / Cryo-CMOS electronics
Deliverable
production ML models | product features | infrastructure
Required skills
Power delivery network architecture, IR drop analysis, voltage droop mitigation, simultaneous switching noise reduction, ground bounce analysis, return-current behavior modeling, electromagnetic coupling mitigation, transmission-line effects analysis, silicon-package-board co-design, advanced packaging (2.5D/3D integration, chiplets), mixed-signal ASIC design, simulation-to-measurement correlation, cross-functional hardware program leadership
Preferred skills
AI tool utilization for performance modeling and task automation, familiarity with Cryo-CMOS circuits, cryogenic electronics, superconducting systems, advanced instrumentation
Technologies
Synopsys RaptorX, Ansys HFSS, SIwave, Cadence Clarity, PowerSI, Keysight ADS, Spectre, HSPICE
Responsibilities
Architect and optimize power delivery networks spanning on-chip grids to board-level distribution; Develop isolation strategies for coexistence of digital switching with sensitive analog/RF/qubit-control signals; Lead analysis and mitigation of switching noise, crosstalk, and mixed-signal interference; Drive silicon-package-board co-design activities; Establish design methodologies, validation plans, and signoff criteria; Correlate simulation results with laboratory measurements; Provide technical leadership for critical architecture decisions
Seniority
Senior/Principal, hands-on IC with strategic oversight
