Senior PCIe IP Design Verification Engineer
Core
Lead verification of complex Peripheral Component Interconnect Express (PCIe) Bridge IP flows, defining strategies and test plans to ensure quality.
Role type
Senior IC verification engineer (PCIe IP)
Builds
PCIe Bridge IP
Domain
Semiconductor hardware design / IP verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
UVM, System Verilog, Python, random-stimulus generation, coverage-driven verification, generative AI application, technical leadership, cross-team coordination, pre-silicon verification, IP/subsystem/SOC level verification
Preferred skills
Generative AI for verification tasks
Technologies
UVM, System Verilog, Python
Responsibilities
Own or lead verification of complex PCIe Bridge IP flows; Develop UVM-based verification environments and run/debug simulations; Innovate to improve verification efficiency through methodologies or tools; Apply industry leading generative AI solutions to verification work; Share expertise and support the growth and development of others through coaching, mentorship, and collaboration
Seniority
Senior, hands-on IC with technical leadership
