Principal Silicon Design Verification Engineer
Core
Own development of C/C++ test content, pre-silicon verification strategy, and SystemVerilog/UVM environments for security IP blocks and SoC integration.
Role type
Principal Silicon Design Verification Engineer
Builds
Production verification environments and test content for secure boot, key management, and processor/bus interactions
Domain
Semiconductor hardware design verification (Silicon DV)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
C/C++ programming, SystemVerilog, UVM, constrained-random testing, formal verification, gate-level verification, coverage signoff, Python scripting, FPGA prototyping, hardware debugging
Preferred skills
Security IP knowledge, AMBA protocols, emulation, post-silicon validation, assembly/startup code, JTAG
Technologies
SystemVerilog, UVM, C, C++, Python, Makefiles, linker scripts, FPGA, JTAG
Responsibilities
Develop C/C++ test content for subsystem and SoC levels, architect and extend SystemVerilog/UVM environments, drive coverage signoff, mentor engineers, improve verification efficiency via automation
Seniority
Principal, hands-on IC with mentorship
