ASIC Design Engineer
Core
Define and architect high-performance hardware blocks for next-generation networking ASICs, performing micro-architecture development and RTL design to achieve maximum performance, throughput, and power efficiency.
Role type
Senior IC ASIC Design Engineer (Networking)
Builds
High-performance networking ASICs supporting advanced protocols and high-speed data processing
Domain
Networking hardware / ASIC design
Deliverable
production ML models | product features
Required skills
Verilog RTL coding, digital logic design, micro-architecture development, timing closure, high-speed serial interfaces, multi-clock domain design, clock domain crossing (CDC), ASIC debugging
Preferred skills
Synopsys Design Compiler, Verplex LEC, SpyGlass, high-performance memory subsystems, networking protocols (Ethernet, FCoE)
Technologies
Verilog, Synopsys Design Compiler, Verplex LEC, SpyGlass
Responsibilities
Define and architect high-performance hardware blocks for next-generation networking ASICs; Develop and implement Verilog RTL code for complex ASIC designs; Collaborate with verification teams to create test plans and support debugging; Work with physical design engineers to develop timing constraints and ensure successful implementation; Analyze and resolve timing violations and perform timing closure activities; Participate in design reviews, debugging, and optimization activities throughout the ASIC development lifecycle
Seniority
Mid-Senior, hands-on IC
