Signal Integrity Engineer
Core
Perform high-speed ASIC PAM4 SerDes and system-level signal and power integrity analysis for cutting-edge networking product design.
Role type
Senior IC Signal Integrity Engineer (High-Speed SerDes)
Builds
High-speed networking ASICs and PCBs with PAM4 SerDes channels
Domain
Networking hardware, High-speed digital design
Deliverable
production ML models | product features
Required skills
Signal Integrity analysis, ASIC PAM4 SerDes design, Channel margin analysis (COM), PCB timing analysis, DVT measurements, PLL design and debug, PCB stack-up design
Preferred skills
200G ASIC PAM4 experience, CAD tools (Ansys HFSS, SIwave, ADS, Allegro, Sigrity, MATLAB), Lab equipment operation (oscilloscopes, VNA, TDR, Spectrum Analyzers), Coefficient tuning, TP1A measurements
Technologies
PAM4, SerDes, 56G/112G/200G, ASIC, PCB, Ansys HFSS, SIwave, ADS, Allegro, Sigrity, MATLAB
Responsibilities
Perform COM channel margin analysis to provide design trade-offs; Correlate simulation results with measurements to improve model accuracy; Perform PCB timing analysis and develop layout/SI design rules; Tune ASIC PAM4 SerDes parameters to improve design margins; Perform SI DVT measurements and correlate with simulations.
Seniority
Senior, hands-on IC
