CPU Load/Store and Core Caches Design Engineer
HybridVisa sponsorship offered
Core
Designing load/store and core cache subsystems for next-generation processors, influencing microarchitectural decisions from specification to RTL implementation.
Role type
Senior IC CPU RTL Design Engineer
Builds
High-quality CPU IP blocks (load/store and cache) for Arm processors
Domain
Semiconductor / CPU Architecture
Required skills
RTL design (SystemVerilog/Verilog), microarchitecture development, digital design principles (pipelining, timing, power), hardware design lifecycle management, PPA trade-off analysis
Preferred skills
CPU load/store/cache design (coherency, memory ordering, virtual memory), synthesis and timing analysis, Python/C/C++ scripting, technical review and mentoring
Technologies
SystemVerilog, Verilog, Python, C, C++
