Machine Learning Hardware Engineer (HW/SW Co-Design)
Core
Architect and co-design machine learning models with traders, quantitative researchers, and software engineers, accounting for hardware constraints such as latency budgets, resource limits, and numerical precision.
Role type
Senior IC machine learning hardware engineer (HW/SW co-design)
Builds
Custom hardware solutions for ML inference in latency-sensitive systems
Domain
Financial trading / Machine Learning / Hardware Acceleration
Deliverable
production ML models
Required skills
ML model mapping to FPGAs/ASICs, VHDL/SystemVerilog, HLS tools, ML-to-hardware frameworks, neural network architectures, inference optimization, quantization, Python, C++, ML compiler infrastructure
Preferred skills
Functional verification methodologies, latency-sensitive system background, emerging research in neural architecture search
Technologies
PyTorch, TensorFlow, MLIR, TVM, XLA, hls4ml, FINN, Vitis AI, SystemVerilog, UVM, Cocotb
Responsibilities
Translate ML model requirements into architectural decisions, implement and verify ML inference solutions from proof of concept through production, evaluate emerging research to improve systems
Seniority
Senior, hands-on IC
