FPGA Digital Design Engineering Intern (January 2027) (4-16 months)
Core
Design custom IP and maintain FPGA code for Kepler's optical satellite constellation and ground stations to enable real-time space communications.
Role type
FPGA Digital Design Engineering Intern
Builds
Real-time on-orbit connectivity for critical missions via optical data relay constellation
Domain
Aerospace / Satellite Communications
Deliverable
production ML models | product features
Required skills
Verilog, SystemVerilog, VHDL, FPGA design, RTL coding, high-speed interfaces (JESD204b, 10G Ethernet, Aurora), sensor/communication interface support (SPI, I2C, UART)
Preferred skills
DSP algorithms, C++, embedded programming, scripting (bash, Python, Tcl), university design team experience
Responsibilities
Maintain and add functionality to FPGA code base for SDR and SDN; Design custom IP for satellites and ground stations; Add support for new sensors and communication interfaces; Work with high-speed FPGA interfaces
Seniority
Intern
