Power Integrity Engineer
Core
Optimize power distribution networks (PDN) for OSFP transceiver designs to ensure robust, low-noise power delivery for high-speed silicon photonics, DSPs, and retimers in 800G+ modules.
Role type
Power Integrity Engineer (IC)
Builds
High-speed silicon photonics modules (OSFP, QSFP-DD) with integrated DSPs and retimers
Domain
Silicon photonics / High-speed digital interconnects / Power electronics
Deliverable
production ML models | product features
Required skills
PDN impedance modeling, VRM design, decoupling capacitor placement, PCB stackup optimization, simultaneous switching noise (SSN) mitigation, EMI/EMC mitigation, power converter topologies (Buck/Buck-Boost), ESL modeling, SerDes design (50G+), Python/MATLAB scripting
Preferred skills
Thermal co-simulation, low-Dk dielectrics, embedded passives, 1.6T OSFP or CPO prototypes
Technologies
Ansys SIwave, Keysight ADS, Cadence Sigrity, HyperLynx, VNA, oscilloscopes, power analyzers
Responsibilities
Perform PI simulations to model and optimize PDN for OSFP modules; Analyze and mitigate power rail decoupling and bypass capacitor placement; Collaborate on PCB stackups and via optimization to reduce SSN and ground bounce; Validate designs through lab measurements and correlate with simulations; Support signal integrity co-optimization and thermal-PD synergy; Document PI reports and mentor junior engineers
Seniority
Mid-Senior, hands-on IC
