PCB Layout Engineer - AI Compute Hardware
Core
Design and deliver high-speed, high-power, high-density PCBs for AI chips, compute trays, and rack-scale platforms to ensure signal and power integrity.
Role type
Senior IC PCB Layout Engineer (AI Compute Hardware)
Builds
AI accelerator boards, compute trays, backplanes, and rack-scale platforms
Domain
AI Compute Hardware / High-Speed Digital Design
Deliverable
production ML models | product features
Required skills
Cadence Allegro, high-speed differential pair routing, impedance control, BGA placement/routing, PDN design, stack-up planning, DFM/DFT compliance, SI/PI simulation analysis
Preferred skills
5nm/3nm AI ASIC layout, 224G PAM4 routing, fiber weave effect mitigation, OCP Open Rack form factors, EMI/EMC design, power integrity simulation tools
Technologies
Cadence Allegro, PCIe Gen5/6, CXL, Ethernet 112G/224G, DDR5, Megtron 6/8/9, TU-953Q, Ansys SIwave, Cadence Sigrity
Responsibilities
Own PCB layout from floorplanning to Gerber release for complex multi-layer boards; Design high-speed interfaces and controlled impedance routing; Plan stack-ups and place/route complex BGA packages; Design power delivery networks (PDN); Ensure DFM/DFT/DFA compliance and coordinate with mechanical engineers; Lead design reviews with JDM/ODM partners; Support bring-up, debug, and signal probing
Seniority
Senior, hands-on IC
