Principal Product Engineer - In-Design Physical Verification (DRC/FILL)
Core
Technical expert enabling and supporting in-design Physical Verification (PV) solutions for advanced semiconductor designs, focusing on DRC, Fill, and LVS methodologies.
Role type
Senior IC Product Engineer (Physical Verification)
Builds
Leading-edge physical verification solutions for advanced semiconductor designs
Domain
Semiconductor / EDA / Physical Verification
Required skills
Physical Verification methodologies (DRC, Fill, LVS), Cadence Innovus, advanced node implementation (16nm/14nm FinFET), customer-facing technical support, rule deck validation, Tcl/Python/Perl scripting (via careerplan.io/jobs/R56582-principal-product-engineer-in-design-physical-verification-drcfill-at-cadence)
Preferred skills
Foundry enablement, Physical Verification rule deck development, design service experience, automation flows
Technologies
Cadence Innovus, Pegasus/PVS, Calibre ICV
Responsibilities
Support customers in deploying and optimizing in-design PV flows; debug and resolve complex PV issues; collaborate with foundries to validate rule decks; interface with R&D and field teams to drive product enhancements; develop automation flows to improve verification coverage and turnaround time.
Seniority
Senior, hands-on IC
