Firmware Engineer II
Core
Design and implement firmware for high-speed SERDES physical layer IP, covering architecture, implementation, verification, and customer deployment.
Role type
Firmware Engineer II (Physical Layer IP)
Builds
High-speed SERDES IP for wireline communication protocols
Domain
Semiconductor / High-speed serial-link protocols
Required skills
C/C++, Python, firmware architecture, firmware implementation, firmware verification, FuSa compliant firmware development, post-silicon debugging, IP debugging
Preferred skills
Digital signal processing, mixed signal circuit design, silicon validation process, digital verification environments, FuSa compliance
Technologies
C, C++, Python
Responsibilities
Collaborate with PHY digital and mixed signal architects on firmware functions and sequences; Build system-level prototype control software for adaptation and equalization algorithms; Implement firmware features and work with verification teams; Develop and execute test plans for FuSa compliant firmware; Support post-silicon testing and implement FW improvements; Debug IP issues during customer deployment and provide hot fixes; Create and maintain firmware design and compliance documentation.
