Lead Design Engineer(Virtual Solution)
Core
Design and develop system-level AVIP solutions for emulation/prototyping platforms and build integrated Accelerated Verification IP environments for complex SoC validation.
Role type
Lead Design Engineer (Verification & Emulation)
Builds
Accelerated Verification IP environments, testbenches, and system-level validation flows for emulation/prototyping platforms.
Domain
Semiconductor verification, emulation, and high-speed protocol integration.
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog/Verilog, C/C++, high-speed protocols (PCIe/CXL/AMBA/UCIe/Ethernet), system-level AVIP design, emulation platform integration, testbench development, bare-metal validation, debugging complex system issues.
Preferred skills
Palladium/Protium platform experience, UVM framework knowledge, Qemu/Gem5 familiarity, multi-language environments (SV/C++/Python), AI/ML techniques in verification.
Technologies
Palladium, Protium, SystemVerilog, Verilog, C, C++, PCIe, CXL, AMBA, UCIe, Ethernet, UVM, Qemu, Gem5.
Responsibilities
Design and develop system-level AVIP solutions for emulation/prototyping platforms; Build and integrate Accelerated Verification IP environments for complex SoC and subsystem validation; Develop end-to-end verification flows including AVIP integration, testbench and system modeling, and bare-metal/driver-level validation; Optimize solutions for performance, scalability, and emulation efficiency; Develop custom test cases, tools, and automation to enable advanced use models; Work closely with cross-functional teams to debug and resolve system-level issues; Support customer enablement, including bring-up, debug, and solution deployment.
Seniority
Senior, hands-on IC
