Sr Principal Design Engineer (Chiplet Solutions)
Core
Leading-edge IP and Chiplet Solutions development for High-Tech Markets including Physical AI, DataCentre, and High Performance Computing.
Role type
Sr Principal Design Engineer (Chiplet Solutions)
Builds
Next generation Chiplets and System IP for customers in consumer, hyperscale computing, 5G, automotive, aerospace, and health sectors.
Domain
Semiconductor / Electronic Design Automation (EDA) / Chiplet Architecture
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Verilog RTL Design, Metric Driven Verification (MDV), Front-end design tools (LINT, Synthesis, CDC Analysis), SoC Architecture and Development, Technical Team leadership
Preferred skills
AMBA, PCIe, CXL & UCIe protocols, Quality processes (ISO-9001 & ISO-26262)
Technologies
UCIe, PCIe, Ethernet, USB, NPU, Audio, Vision, CPUs, ISP, Silicon Monitors, NoCs
Responsibilities
Technical leadership of complex Silicon programs, define next generation Chiplets, integrate Cadence and partner IP, lead RTL/Testbench/Formal/Trial Synthesis activities, plan Chiplet Subsystems milestones, lead cross-functional technical meetings, represent Cadence at industry conferences
Seniority
Sr Principal, hands-on IC with leadership
