Junior Layout Design Engineer (Trainee)
Core
Entry-level IC mask design trainee creating full chip floor plans, schedules, hookups, and verification for analog and mixed-signal ICs.
Role type
Junior IC Layout Design Engineer (Trainee)
Builds
Full chip projects for advanced analog and mixed-signal ICs
Domain
Semiconductor / IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Computer proficiency, spatial awareness, puzzle solving, detail-oriented, memory retention, team collaboration
Preferred skills
Computer programming/coding, Linux proficiency
Technologies
Cadence Virtuoso Layout XL, Calibre (LVS, DRC, Latchup, Antenna Verification)
Responsibilities
Create full chip floor plans, plan schedules, perform hookup and verification, route sub-cells and blocks, conduct tape out
Seniority
Entry-level, on-the-job training