SoC Architect, Coherent Interconnect
Core
Designing and implementing high-performance, low-power coherent interconnect architectures (cache, NoC, interfaces) for Samsung's premium SoCs to enable on-device machine learning and advanced system applications.
Role type
Senior IC SoC Architect (Coherent Interconnect)
Builds
Proprietary coherent interconnects and memory controllers for Exynos SoCs
Domain
Semiconductor / High-performance computing / Mobile SoC architecture
Deliverable
production ML models | product features
Required skills
SoC architecture, coherent interconnect design, cache subsystems, Network-on-chip (NoC) design, high-speed interface protocols, system-level design optimization, C/C++/Python/Verilog/VHDL
Preferred skills
Memory subsystem design (JEDEC standards), on-device ML for LLMs, Android ecosystem, Arm Architecture
Technologies
AXI, ACE, CHI, PCIe, USB, MESI, MOESI, LPDDR, HBM, DDR
Responsibilities
Design coherent interconnect architectures including cache coherence protocols and NoC; Develop and validate interconnect IP blocks; Optimize interconnect performance, power, and area; Collaborate with global system architects and software teams to define SoC architectures.
Seniority
Senior, hands-on IC
