RTL Design Lead Engineer
Core
Technically managing design and development of Storage IPs for high-speed peripheral bus standards.
Role type
Senior RTL Design Lead Engineer (Storage IP)
Builds
Storage controller IPs based on NVMe, UFS, PCIe, and CXL standards
Domain
Semiconductor / Storage Solutions / System LSI
Deliverable
production ML models | product features
Required skills
Project management, RTL coding (Verilog/System Verilog/VHDL), Design QC (Lint/CDC/DFT), Synthesis and timing analysis, Storage controller architectures, Bus Architectures (AXI/AHB), NOC, ARM CPU architectures, Functional design documentation, ECO development, High-speed serial protocols (PCIe, NVMe, UFS)
Preferred skills
RTL integration tools (Magillem), FPGA-based development
Technologies
VCS, NCsim, Verdi, Spyglass, Synopsys Design Compiler (DC), Magillem
Responsibilities
Prepare project and risk management plans for cutting-edge designs, Interface with cross-functional teams (Verification, Validation, SoC, FW), Ensure design quality using Lint and CDC checks, Perform synthesis, area, and power optimization, Develop timing constraints (SDC) and ECO scripts
Seniority
Senior, hands-on IC
