Mixed Signal IP Integration Engineer – New Grad
Core
Design and integration of custom mixed-signal macros within an ASIC flow for next-generation high-baud-rate optical modems.
Role type
New Grad mixed-signal IP integration engineer
Builds
Custom mixed-signal macros for optical modems
Domain
Semiconductor / High-speed optical networking
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog design principles, schematic capture, layout, extraction, pre- and post-layout analog simulation, design rule checking, layout versus schematic verification, Verilog/RTL, place-and-route, static timing analysis, Cadence Design Systems tools, Cadence Innovus, Synopsys Integrated Circuit Compiler II
Preferred skills
Python scripting, Cadence Skill language
Technologies
Cadence Design Systems, Cadence Innovus, Synopsys Integrated Circuit Compiler II, Verilog, SPICE
Responsibilities
Generate representations of mixed-signal blocks for the digital design team including Verilog, LEF, Liberty timing files, documentation, and layout files; Develop understanding of macro-level standard cell interfaces to facilitate analog-digital timing handoff and static timing analysis; Contribute to digital integrated circuit design using standard cell libraries and develop design-for-test solutions and models.
Seniority
New Grad, entry-level IC design