Junior Verification Engineer

Jerusalem, Israel💼 Full-time🗓 2026-09-04 → 2026-09-26

Core

Develop and verify high-speed SerDes IP (10Gbps to 100Gbps+) for PCIe, Ethernet, and other interfaces, focusing on digital/analog design, DSP pipelines, and firmware-hardware co-verification.

Role type

Junior Design Verification Engineer (SerDes IP)

Builds

High-speed SerDes physical layer technology for data transmission

Domain

Semiconductor / Hardware Verification / High-Speed Interfaces

Deliverable

Required skills

Digital design, Computer architecture, Software programming, Root cause analysis, SystemVerilog/UVM, Python

Preferred skills

Mixed-signal/analog simulation concepts, High-speed protocols (PCIe, Ethernet), RTL design experience, AI-assisted tooling

Technologies

SystemVerilog, UVM, Python, AI-assisted tools

Responsibilities

Constrained-random and coverage-driven verification of complex high-speed SerDes mixed-signal IP, Validation of DSP datapaths, FW/HW joint verification, Developing advanced verification environments

Seniority

Junior, entry-level IC

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About Altera

At Altera™, our independence as the world's largest pure-play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry-leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets including AI, cloud, networking, communications, automotive, and edge computing. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape