DSP ASIC Verification Engineer - Optical Transmission Systems
Core
Design and execute digital verification for architectural functional blocks within Ciena's WaveLogic optical transmission product family to ensure reliable functionality.
Role type
Senior IC ASIC verification engineer (optical transmission)
Builds
WaveLogic family of products for high-performance global telecommunications networks
Domain
Optical transmission systems / High-speed connectivity
Deliverable
production ML models | product features
Required skills
SystemVerilog UVM, SVA, C++, functional coverage modeling, regression analysis, EDA verification tools, formal methods, coherent DSP architectures, OTN/FlexO/B100G/Ethernet protocols, Git, Jira
Preferred skills
Python, Make, Bash, C, formal verification methods
Technologies
SystemVerilog, UVM, C++, Python, Git, Jira, EDA tools
Responsibilities
Design and execute verification activities for architectural functional blocks; Analyse architecture and functional requirement specifications; Develop and implement validation strategies using simulation, formal methods, and coverage techniques; Create and integrate verification environments including test benches, agents, scoreboards, and test scenarios; Define and implement functional coverage models; Perform coverage-driven verification, analyse regression results, and debug failures
Seniority
Mid-Senior, hands-on IC