System Level Test (SLT) Content Development and Debug Engineer
Core
Define and execute validation methods and test plans for system-level test and product platform validation of FPGA and multi-chip packages.
Role type
System Level Test (SLT) Content Development and Debug Engineer
Builds
Automated verification flows, regression scripts, and test plans for FPGA, transceiver, and multi-chip packages.
Domain
Semiconductor / FPGA / Hardware Validation
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
System-level test planning, automated test development, data analysis, root cause debugging, cross-functional collaboration, hardware characterization
Preferred skills
Test content and vector generation, test automation framework maintenance, manufacturing test methodology definition, Verilog/VHDL, Quartus Prime, TCL, Python
Technologies
FPGA, Transceiver, Multi-chip packages, Quartus Prime, TCL, Python, Verilog, VHDL
Responsibilities
Develop test plans, methods, execution, data analysis, builds automation and regression scripts; Understand IP subsystem validation requirements and coverage needs; Perform debug to root cause product issues and execute workarounds; Evaluate integrated system performance and characterize device functionality; Contribute to product health indicators and test hole reduction; Create platform validation documentation including risk assessments and user acceptance tests.
Seniority
Mid-Senior, hands-on IC
