R&D Engineer, IC Design
Core
Write and maintain assertions and design verification (DV) tests for chip-level and block-level models, create netlists, and use AI to generate real-number models.
Role type
IC Design R&D Engineer
Builds
Chip-level and block-level models and verification test suites
Domain
Semiconductor IC Design
Deliverable
production ML models
Required skills
Verilog/SystemVerilog, Python, real-number modeling, AI-assisted development, Linux, Cadence Virtuoso, Git, JIRA
Preferred skills
AI-assisted development tools, cross-team collaboration
Technologies
Cadence Virtuoso, Python, Git, JIRA, Linux, Windows
Responsibilities
Write and maintain assertions and DV tests for chip-level and block-level models; Gather design data from circuit designers; Create netlists and use AI to create models; Write tests to verify the models; Write code to automate tasks
