Infrastructure AI/ML Engineer for Memory Design, Characterization, and Yield Optimization
Core
Lead Agentic AI Infrastructure development for memory design, characterization, and yield optimization workflows.
Role type
Senior IC Infrastructure AI/ML Engineer
Builds
Agentic AI workflows, multi-agent orchestration frameworks, and predictive yield models for embedded memory
Domain
Semiconductor memory design, DFT, and AI systems engineering
Deliverable
production ML models
Required skills
Memory design and characterization, DFT and silicon yield analysis, multi-agent AI orchestration, LLM application architecture, EDA tool integration, Python and TCL, microservices architecture, Kubernetes, vector databases
Preferred skills
Compute-in-memory design, LangGraph, Model Context Protocol (MCP), System Verilog, UVM
Technologies
Python, TCL, LangGraph, Docker, Kubernetes, Synopsys, Cadence, Siemens EDA, Vector Databases
Responsibilities
Architect and deploy distributed multi-agent AI frameworks for memory design; Integrate LLM-driven agent pipelines with EDA suites; Develop ML models for scan failure classification; Build predictive yield models using Fab process and E-test data; Partner with design leads to modularize hardware engineering methodologies
Seniority
Senior, hands-on IC
