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FPGA Design Verification Engineer

Regus, Madhapur💼 Full-time🗓 2026-08-27 → 2026-09-26

Core

Intern role supporting FPGA verification activities for next-generation Altera FPGA products, specifically focusing on high-speed transceiver and ethernet protocols.

Role type

Intern FPGA Design Verification Engineer

Builds

Next-generation FPGA IPs and products

Domain

Semiconductors / FPGA / High-speed protocols

Deliverable

production ML models | product features

Required skills

VLSI design knowledge, HDL languages (VHDL, Verilog, SystemVerilog), scripting (Tcl, Perl, Python), FPGA tools (Quartus, Vivado)

Preferred skills

Experience in high-speed design challenges

Responsibilities

Support ongoing and upcoming verification projects, develop verification and debugging solutions, document technical specifications, collaborate with verification team members, present updates to stakeholders

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