FPGA SW Validation Engineer (PR)
Core
Validates and researches Compiler optimizations, Partial Reconfiguration (PR) flow, and debug features using Quartus and Altera FPGA hardware.
Role type
Senior IC FPGA SW Validation Engineer
Builds
Compiler/PR validation strategies and resolved customer issues
Domain
Semiconductor / FPGA Design
Required skills
FPGA/ASIC Design, RTL/HDL design and verification, VHDL/Verilog/SystemVerilog, FPGA Devices (Agilex, Virtex), Quartus/Vivado, SignalTap/ChipScope, Simulation/Verification (QuestaSim, VCS, XCelium, STA), Unix/Linux, Scripting (Shell, Perl/TCL, Python), PCIe/Ethernet/Avalon/AXI/HPS protocols
Preferred skills
None stated
Technologies
Quartus, Altera FPGA, Agilex, Virtex, SignalTap, System Console, QuestaSim, VCS, XCelium, PCIe, Ethernet, Avalon, AHB, AXI, HPS
Responsibilities
Validate and research Compiler optimizations and Partial Reconfiguration (PR) flow; Create and verify HDL designs on FPGA hardware; Regress designs for Quality of Result (QoR) and monitor performance; Collaborate with cross-functional teams to improve validation strategies and resolve customer issues
Seniority
Senior, hands-on IC