Place and Route Design Automation Engineer
Core
Developing and supporting automated Place & Route (P&R) tools, flows, and methodologies for next-generation FPGA silicon development.
Role type
Place & Route Design Automation Engineer
Builds
Automated P&R flows and tool enhancements for FPGA silicon
Domain
Semiconductor design automation / FPGA
Deliverable
production ML models | product features | infrastructure
Required skills
P&R algorithms and methodologies, EDA vendor tools (Synopsys, Cadence), Tcl/Perl/Python scripting, Unix/Linux development, physical design fundamentals (floorplanning, placement, clocking, routing, STA), debugging tool/flow issues
Preferred skills
Cross-functional collaboration, multi-geo team support
Technologies
Synopsys, Cadence, Tcl, Perl, Python, Unix/Linux
Responsibilities
Develop new P&R methodologies and tool enhancements, maintain and improve existing automation flows, provide end-user support and debugging, develop automation scripts, evaluate new tool capabilities, identify and optimize flow bottlenecks, document methodologies and usage guidelines
Seniority
Mid-level, hands-on IC
