Staff/ Senior Staff NPI Debug Engineer
Core
Senior technical leader orchestrating cross-functional taskforces to resolve critical NPI hardware escalations, focusing on analog, mixed-signal, and power delivery challenges for FPGA products.
Role type
Staff/ Senior Staff NPI Debug Engineer
Builds
FPGA solutions for AI, cloud, networking, and edge markets
Domain
Semiconductor / FPGA / Hardware Debug
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
hardware debug, NPI engineering, product/yield engineering, system validation, fault tree definition, design of experiments (DOE), yield analysis, statistical data review, Python, JMP, failure analysis (FA), analog/mixed-signal debug, lab equipment operation
Preferred skills
Master's or PhD in Electrical Engineering, Electronics, or Physics, advanced fault isolation techniques, exceptional technical communication
Technologies
Python, JMP, ATE, simulation tools, failure analysis tools
Responsibilities
Lead cross-functional 'tiger teams' to solve critical NPI blockers involving analog, power, or signal integrity; define debug strategies and assign ownership across design, test, and manufacturing; synthesize complex data from simulation, ATE, and FA to identify root causes; lead yield analysis activities including pareto analysis and parametric shift review; present risk assessments and recovery plans to executive leadership; guide experimental builds and validation of engineering fixes.
Seniority
Staff, hands-on IC with strategic leadership